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features ? 4-bit harvard architecture 4k 8-bit application rom 256 4-bit ram 32 16-bit eeprom 10 bi-directional i/os 4 external interrupt inputs (sso20) 8 interrupt levels 2 8-bit multifunction timer/counter interval timer with watchdog two-wire interface (twi) voltage supervisor on-chip rc oscillator on-chip crystal oscillator benefits contactless power supply and communication interface power management for contactless and battery power supply shift-register-supported modu lator and demodulator stages low power consumption active mode < 300 a at 2v and 1 mhz system clock frequency (2 s instruction cycle) power-down mode < 1 a supply voltage 2.0v to 6.5v high-level language programming in qforth operating speed: 1 s to 10 s instruction cycle (2 s at v dd = 2v) 1. description the U9280M-H ic is a multi-chip module for remote control and contactless id sys- tems. it consists of the atar092 microcontroller and u3280m transponder interface circuit with eeprom. a coil connected to th e transponder interface serves as a wire- less bi-directional communication interf ace as well as a power supply for the microcontroller and the interface. as a t ransponder, the device is supplied by a mag- netic rf field applied at the coil. for ir- or rf-transmitter applications, it can be supplied by a battery. the microcontroller s upports, with its built-in timers, a wide range of ir- and rf-transmission modes such as burst-modulation modes, pwm-, nrz-, manchester- and bi-phase coding. microcontroller with transponder interface U9280M-H rev. 4591b?rfid?09/05
2 4591b?rfid?09/05 U9280M-H figure 1-1. block diagram 2. pin configuration figure 2-1. pinning sso20 damping stage 512-bit eeprom memory U9280M-H transponder interface coil1 coil2 v ss atar092 microcontroller osc2 osc1/rosc bp60/t3o ram rectifier vdd field/gap detect vbatt mod ngap bp42/ t2o bp63/t3i bp23 bp53/int1 bp40/ sc/int3 bp50/int6 bp41/ vmi/ t2i bp43/ sd/int3 timer/ counter c biphase modulator rom voltage monitor reset bp20/nte serial interface clock extractor fc power management 4-bit cpu core mcl i/o-ports serial interface modulator/ demodulator oscillators clock management 1 vdd bp40/sc/int3 bp50/int6 bp53/int1 osc1/rosc osc2 bp60/t3o bp41/vmi bp43/sd/int3 bp42/t2o vss bp63/t3i/int5 bp20/nte bp23 coil1 vbatt mod coil2 ngap U9280M-H 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 fc
3 4591b?rfid?09/05 U9280M-H table 2-1. pin description pin symbol function 1 coil1 coil input 1, pin to connect an lc antenna for communication and field supply 2 coil2 coil input 2, pin to connect an lc antenna for communication and field supply 3 vbatt power-supply voltage input to connect a battery 4vdd power-supply voltage for the microcontroller and eeprom. at this pin a capacitor (0.5 f to 10 f) must be connected to buffer the voltage during field supply and to block the v dd of the microcontroller. 5 bp40/sc/int3 i/o-port line/serial clock line/int3 input (falling edge sensitive) 6 bp53/int3 i/o-port line/int3 interrupt input (falling or rising edge sensitive) 7 bp50/int6 i/o-port line/int6 interrupt input (falling or rising edge sensitive) 8 osc1/rosc oscillator- or external system-c lock input/input for rc-oscillator resistor 9 osc2 oscillator output 10 bp60/t3o bi-directional i/o-line/timer 3 output/modulator output 11 bp63/t3i/int5 i/o-port line/int5 interrupt input/timer 3 input/demodulator input 12 bp20/nte bp20-i/o-port line/test mode input. this input is used to control the test modes. during por it must not be connected with a low impedance to v dd. 13 bp23 i/o-port line 14 bp41/vmi i/o-port line/voltage monitor input/timer 2 input 15 bp42/t2o i/o-port line/timer 2 output/modulator output 16 bp43/sd/int3 i/o-port line/serial data line/int3 input (falling edge sensitive) 17 vss circuit ground 18 fc field clock output of the clock extractor 19 mod modulation input - front end. must be connected to the modulator output t2o. 20 ngap gap detect output - front end. must be connected to the de modulator input t3i.
4 4591b?rfid?09/05 U9280M-H 3. functional description the U9280M-H multi-chip module contains a mi crocontroller and a transponder ic mounted in a single package. everything necessary for remote control and wireless identification systems is integrated: inputs to connect keys, outputs to control an ir- or rf transmitter and to drive indica- tor leds, an eeprom to store key code and iden tifiers, and an interface for contactless communication and a power supply. the u3280m is a transponder interface consisting of an analog front end for contactless data communication and power supply, and a serial 5 12-bit eeprom. in addition, it includes power management to switch the battery or magnetic-field power supply. for modulation and demodu- lation of the magnetic field, the device has input and output pins to connect the microcontroller. the mod, ngap and fc pins can be connected externally to the modulator, demodulator and timer i/o pins of the microcontroller. access to the eeprom is possibl e via a two-wire serial interface. the atar092 microcontrollers are equipped with compatible two-wire serial interface to communicate with the u3280m. in the U9280M-H the serial interfaces of the transponder interface and the microcontroller are linked internally. 3.1 atar092 the atar092 microcontroller is a member of the atmel?s 4-bit single-chip microcontroller family. it is especially designed for remote-control applic ations. it consists of an advanced stack-based 4-bit cpu core with 4k rom, 256 nibble of ram and on-chip peripherals. the cpu is based on the harvard architecture and contains an interrupt controller with 8 prioritized interrupt levels. the peripherals include parallel i/o ports, two 8-bit programmable multifunction timer/counters, a two-wire serial interface, an interval timer with watchdog function and a voltage supervisor. the serial interface supports, together with the timers, a modulator and demodulator stage for manchester, bi-phase and pulse-width modulation and demodulation. the integrated clock gen- erator contains a rc-, a 32-khz crystal, a 4-mh z crystal oscillator and a programmabl e input to use an external clock. note: in the U9280M-H not all i/o pins of the atar092 are available (see table 2-1 on page 3 ). the microcontroller is fully described in the marc4 atar092 data sheet.
5 4591b?rfid?09/05 U9280M-H figure 3-1. block diagram atar092 3.2 the u3280m transponder interface the transponder interface contains a rectifier stage to rectify the ac from the coil inputs and to supply itself and an additional microcontroller device with power from an lc-resonant circuit at the coil inputs. it is also possible to supply the device via the v batt -input with dc from a battery. the built-in power management switches aut omatically between battery supply (v batt pin) and coil supply. it switches to coil supply if a field is applied at the coil and switches back to battery if the field is removed. the voltage from the coil or the v batt pin is output at the v dd pin to supply the microcontroller device. at the v dd pin a capacitor must be connected to smooth and buffer the supply voltage for the transponder interface and the microcontroller. th is capacitor is also used to buffer the supply voltage during communication (damping and gaps in the field). for communication, a damping-stage and a gap-detect circuitry is on the chip. by means of the damping stage the coil voltage can be modulated to transmit data via the field. it can be con- trolled with the modulator input (mod pin) via the microcontroller. the gap detection circuitry detects gaps in the field and outputs the gap/field signal at the gap detect output (ngap pin). it can be used to receive data via a modulated field a nd to check if a field is applied at the coil. voltage monitor external input marc4 utcm osc1 osc2 i/o bus rom ram 4-bit cpu core 256 x 4 bit v dd v ss data direction + alternate function data direction + interrupt control port 4 port 5 data dir. + alt. function port 6 timer 3 brown-out protect reset clock management timer 1 watchdog timer timer 2 serial interface port 1 p o r t 2 d a t a d i r e c t i o n t2o sd sc t3o t3i bp10 bp13 bp20/nte bp21 bp22 bp23 bp40 int3 sc bp41 vmi t2i bp42 t2o bp43 int3 sd bp50 int6 bp51 int6 bp52 int1 bp53 int1 bp60 t3o bp63 t3i rc oscillators crystal oscillators 4 k x 8-bit vmi with modulator ssi external clock input interval- and 8/12-bit timer 8-bit timer / counter with modulator and demodulator t2i
6 4591b?rfid?09/05 U9280M-H for the storage of data such as key codes, identifiers and configuration bits, a 512-bit eeprom is available on the chip. it can be read and written to by the microcontroller via a twi-compatible two-wire serial interfac e. the serial interface, the eeprom and the micr ocontroller are supplied with the voltage at the v dd pin. that means the microcontroller can read and write to the eeprom if the supply voltage is in the operati ng range. the u3280m contains additional operating m odes to support a wide range of applications. these modes can be controlled via the serial interface. the power management can be switched off by software to disable the automatic switching between battery and field. this sup- ports applications with battery supply only. there is an on-chip bi-phase and manchester modulator. it can be selected and controlled via the serial interface with a special mode control byte. if this modulator is used the external con- nection to the modulator input is not necessary. 3.3 modulation the transponder interface can modulate the magnetic field by a modulator to transmit data to a base station. it modulates the coil voltage by varying the coil?s load. the modulator can be con- trolled via the mod pin. a high level 1 increases the current into the coil inputs and damps the coil voltage. a low level 0 decreases the current and increases the coil voltage. the modulator generates a voltage stroke of about 2 v pp at the coil. a high level at the mod input makes the maximum of the field energy available at v dd . during a reset a high level at the mod input causes the optimum conditions for starting the device and charging the capacitor at v dd after the field is applied at the coil. 3.3.1 digital input to control the damping stage (mod) mod = 0: coil undamped mod = 1: coil damped v cms = v cid : modulation voltage stroke at coil inputs note: if the automatic power management is disabled the internal front end v dd is limited at v ddc . in this case the value v ddc must be used in the formula above. 3.4 field clock the field clock extractor of the interface makes t he field clock available for the microcontroller. it can be used to supply timer inputs to synchroni ze modulation and demodulation with the field clock. v coil_peak v dd 2v cms + v cu == v coil_peak v dd 2 v cd ==
7 4591b?rfid?09/05 U9280M-H 3.5 gap detect the transponder interface can also receive data. the base station modulates the data with short gaps in the field. the gap-detection circuit de tects these gaps in the magnetic field and outputs the gap/field signal at the ngap pin. a high level indicates that a field is applied at the coil and a low level indicates a gap or that the field is off. the microcontroller must demodulate the incom- ing data stream at one of its inputs. 3.5.1 digital output of the gap detection stage (ngap) ngap = 0: gap detected/no field v coil_peak = v fdoff ngap = 1: field detected v coil_peak = v fdon note: no amplifier is used in the gap detection stage. a digital schmitt trigger ev aluates the rectified and smoothed coil voltage. 3.6 wake-up signal if a field is applied at the coil of the transponder interface the microcontroller can be woken up with the wake signal at the ngap pin. for that purpose the ngap pin must be connected to an interrupt input of the microcontroller. a high leve l at the ngap output indicates an applied field and can be used as a wake signal for the microcon troller via an interrupt. if no battery voltage is available at v batt the controller starts with a power-on-reset after the voltage of the buffer capac- itor at v dd is loaded by the field above the power-on-reset level. the wake signal is generated if the power management switches to field supply. the field detec- tion stage of the power management has low-pass characteristics to avoid the generation of wake signals and unnecessary switching between battery and field supply in case of interfer- ences at the coil inputs. 3.7 u3280m signals and timing figure 3-2. modulation v cu v cd v cms mod coil inputs
8 4591b?rfid?09/05 U9280M-H figure 3-3. gap detection and battery to field switching 3.8 power supply the u3280m has a power management that handles two power-supply sources. normally, the ic is supplied by a battery at the v batt pin. if a magnetic field is a pplied at the lc-resonant circuit of the device the field detection circuit switches from v batt to field supply. during field supply the v dd voltage is limited to 3v. the v dd pin is used to connect a capacitor to smooth the voltage from the rectifier and to buffer the power when the field is modulated by gaps and damping. the eeprom and the microcon- troller always operate with the voltage at the v dd pin. 3.8.1 automatic power management there are different conditions to switch from the battery to field generated voltage and vice versa. figure 3-4. switch conditions for power management v fdon v fdoff t fbs t bfs coil supply if automatically power management is enabled battery supply battery supply coil inputs ngap field clock fc power management 1. edge used as wakeup signal t fgap1 t fgap0 v fdon v fdoff t fbs t bfs coil supply if automatically power management is enabled battery supply battery supply coil inputs ngap field clock fc power management 1. edge used as wakeup signal t fgap1 t fgap0 battery supply field supply (v batt ) v coil < v fdon for t > t fbs v coil < v fdoff for t > t fbs
9 4591b?rfid?09/05 U9280M-H the power management switches automatically from battery to field if the rectified voltage (v coil ) from the coil inputs becomes higher than field-on-detection voltage (v fdon) even if no battery voltage is available (0 < v batt < 1.8v). it switches back to ba ttery if the coil voltage becomes lower than the field-off-detection voltage (v fdoff ). the field-detection stage of the power management has low-pass characteristics to suppress noise. an applied field needs a time delay t bfs (battery-to-field switch delay) to change the power supply. if the field is removed from the coil the power management will generate a reset of the microcontroller. 3.8.2 controlling power management via the serial interface the automatic mode of the power management can be switched off and on by a command from the microcontroller. if the automatic mode is switched off the ic is always supplied by the battery up to the next power-on reset or to a switch-on command. the power management-on and -off command must be transferred via the serial interface. if the power management is switched off and the device is supplied from the battery it can com- municate via the field without loading the field. this mode can be used to realize applications with a battery supply if the available fiel d is too weak to supply the ic with power. 3.8.3 buffer capacitor cb the buffer capacitor connected at v dd is used to buffer the supply voltage for the microcontroller and the eeprom during field supply. it smooths the rectified ac from the coil and buffers the supply voltage during modulation and gaps in the fi eld. the size of this capacitor depends on the application. it must be of a dimension so that during modulation and gaps the ripple on the sup- ply voltage is in the range of 100 to 300 mv. during gaps and damping the capacitor is used to supply the device, that means the size of the capacitor depends on the length of the gaps and damping cycles. example: for a supply current of 350 a, 200 mv ripple at v dd table 3-1. buffer capacitor time with no field supply necessary cb 250 s 470 nf 500 s 1000 nf
10 4591b?rfid?09/05 U9280M-H 3.9 serial interface the transponder interface has an serial interfac e to the microcontroller for read and write accesses to the eeprom. in a special mode the seri al interface can also be used to control the bi-phase/manchester modulator or the power management of the u3280m. the serial interface of the u3280m device must be controlled by a master device (normally the atar09x microcontroller) which generates the serial clock and controls the access via the scl- and sda-line. scl is used to clock the data in and out of the device. sda is a bi-directional line used to transfer data into and out of the device. the following protocol is used for data transfers. 3.9.1 serial protocol data states on the sda line changing only while scl is low. changes in the sda line while scl is high will be interpreted as a star t or stop condition. a start condition is defined as a high-to-low transition on the sda-line while the scl-line is high. a stop condition is defined as a low-to-high transition on the sda-lin e while the scl-line is high. each data transfer must be initialized with a start condition and terminated with a stop condition. the start condition wakes the device from standby mode and the stop condition returns the device to stand-by mode. a receiving device generates an acknowledge (a) after the reception of each byte. for that the master device must generate an extra clock pulse. if the reception was successful the receiving master or slave device pulls down the sda-line during that clock cycle. if in transmit mode an acknowledge is not detected (n) by th e interface, it will terminate further data transmissions and will go into rec eive mode. a master device must finish its read operation by a not-acknowledge and then issue a stop condition to place the device into a known state. figure 3-5. serial protocol start condition data valid data change data/ acknowledge valid stop condition scl sda stand- by stand- by
11 4591b?rfid?09/05 U9280M-H 3.9.2 control byte format the control byte follows the start condition and co nsists of the 5-bit row address, 2 mode control bits and the read/not write-bit. 3.9.3 data transfer sequence before the start condition and after the stop condition the device is in standby mode and the sda-line is switched to input with a pull-up resistor. the start condition follows a control byte that determines the following operation. bit 0 of the control byte is used to control the following transfer direction. a 0 defines a write access and a 1 a read access. 3.10 eeprom the eeprom has a size of 512 bi ts and is organized as a 32 16-bit matrix. to read and write data to and from the eeprom the serial interface must be used. the interface supports one and two byte write accesses and one to n-byte read accesses to the eeprom. 3.10.1 operating modes the operating modes of the eeprom are defined via the control byte. the control byte contains the row address, the mode control bits and the read/write bit that is used to control the direction of the following transfer. a 0 defines a write acce ss and a 1 a read access. the five address bits select one of the 32 rows of the eeprom memory to be accessed. for all accesses the com- plete 16-bit word of the selected row is loaded into a buffer. the buffer must be read or overwritten via the serial interface. the two mo de control bits c1 and c2 define in which order the accesses to the buffer are performed: high byte ? low byte or low byte ? high byte. the eeprom also supports autoincrement and autodecrement read operations. after sending the start address with the corresponding mode, consecutive memory cells can be read row by row without transmission of the row addresses. two special control bytes enable the complete initialization of eeprom with a 0 or with a 1. 3.10.2 write operations the eeprom allows 8-bit and 16-bit write operati ons. a write access starts with the start condition followed by a write control byte and one or two data bytes from the master. it is com- pleted via the stop condition from the master after the acknowledge cycle. if the eeprom receives th e control byte, it loads the content of the addressed me mory cell into a 16-bit read/write buffer. after the first data byte has been received the eeprom starts the internal programming cycle. it cons ists of an erase cycle (write ?z eros?) and the write cycle (write ?ones?). each cycle takes about 10 ms. the write cycle is started after the stop condition and the complete buffer is stored back automatically to the eeprom. that means for two-byte write operations, the second byte must be transferred within the erase cycle otherwise only the first byte will be stored in the eeprom and the second byte will be ignored. eeprom address mode control bits read/write starta4a3a2a1a0c1c0 r/wackn start control byte ackn. data byte ackn. data byte ackn. stop
12 4591b?rfid?09/05 U9280M-H 3.10.3 acknowledge polling if the eeprom is busy with an internal write cycle, all inputs are disabled and the eeprom will not acknowledge until the write cycle is finished. this can be used to detect the end of the write cycle. the master must perform acknowledge poll ing by sending a start condition followed by the control byte. if the device is still busy with the write cycle, it will not return an acknowledge and the master has to generate a stop condition or perform further acknowledge polling sequences. if the cycle is complete, it returns an acknowledge and the master can proceed with the next read or write cycle. note: a = acknowledge 3.10.4 write control bytes note: hb: high byte; lb: low byte; r: row address write one data byte start control byte a data byte 1 a stop write two data bytes start control byte a data byte 1 a data byte 2 a stop write control byte only start control byte a stop msb lsb write low byte first a4 a3 a2 a1 a0 c1 c0 r/w row address 0 1 0 byte order lb(r) hb(r) msb lsb write high byte first a4 a3 a2 a1 a0 c1 c0 r/w row address 1 0 0 byte order hb(r) lb(r)
13 4591b?rfid?09/05 U9280M-H 3.10.5 read operations the eeprom allows byte-, word- and current address read operations. the read operations are initiated in the same way as write operations. every read access is initiated by sending the start condition followed by the control byte which contains the address and the read mode. after the device receives a read command it returns an acknowledge, loads the addressed word into the read/write buffer and sends the selected data byte to the master. the master has to acknowledge the received byte if it wants to proceed with the read operation. if two bytes are read out from the buffer the device increments respectively, decrements the word address auto- matically and loads the buffer with the next word. the read mode bits determines if the low or high byte is read first from the buffer and if the word address is incremented or decremented for the next read access. if the memory address limit is reached, the data word address will ?roll over? and the sequential read will continue. the master can terminate the read operation after every byte by not responding with an ack nowledge (n) and by issuing a stop condition. note: a -> acknowledge, n -> no acknowledge 3.10.6 read control bytes note: hb: high byte; lb: low byte, r: row address read one data byte start control byte a data byte 1 n stop read two data bytes start control byte a data byte 1 a data byte 2 n stop read n data bytes start control byte a data byte 1 a data byte 2 a ? data byte n n stop msb lsb read low byte first, address increment a4 a3 a2 a1 a0 c1 c0 r/w row address 0 1 1 byte order lb(r) hb(r) lb(r+1) hb(r+1) ? lb(r+n) hb(r+n) msb lsb read high byte first, address decrement a4 a3 a2 a1 a0 c1 c0 r/w row address 1 0 1 byte order hb(r) lb(r) hb(r-1) lb(r-1) ? hb(r-n) lb(r-n)
14 4591b?rfid?09/05 U9280M-H 3.10.7 initialization after a reset condition the eeprom with the serial interface has its ow n reset circuitry. in sy stems with microcontrol- lers that have their own reset circuitry for pow er-on reset, watchdog reset or brown-out reset, it may be necessary to bring the eeprom into a k nown state independent of its internal reset. this is performed by reading one byte wit hout acknowledging and then generating a stop condition. 3.10.8 special modes by means of special control bytes, the serial interface can be used to control the modulator stage or power management. the eeprom access and the serial interface are disabled in these modes until the next st op condition. if no start or st op condition is generated, the scl and sda line can be used for the modulator stage. scl is used for the modulator clock and sda is used for the data. in that mode, the same conditions for clock and data changing nor- mally are valid. the scl and sda line can be used for continuous bit transfers, an acknowledge cycle after 8 bits must not be generated. 3.10.9 data transfer sequence for bi-phase and manchester modulation: note: after a reset of the microcontroller, it is not known if the transponder interface has been reset, too. it could still be in a re ceive or transmit cycle. to place the se rial interface of the device into a known state, the microcontroller should read one byte from the device without acknowledge and generate a stop condition. 3.11 power-on reset the analog front end starts working with the applied field. the eeprom with the serial interface has its own reset circuitry. (the reset level of the front end is below the reset level of the atar092) the microcontroller has a power-on reset circuitr y with a brown-out detection. one of two reset voltage levels [1.8v/2.0v] can be selected via the software (see the atar092 data sheet). if a fast instruction cycle (< 2 s) is used the higher reset level should be selected. after a watchdog or brown-out detection reset, the serial interface and the eeprom should be reset by reading one byte from the transponder interface device without acknowledging and generation of a stop condition. that places the serial interface and eeprom into a known state. table 3-2. special modes control byte description 1100x111b bi-phase modulation 1101x111b manchester modulation 11xx0111b switch power management off: disables switching from battery to field supply 11xx1111b switch power management on: enables automatically switching between battery and field supply xxxxx110b reserved start control byte ackn bit 1 bit 2 bit 3 ... bit n stop
15 4591b?rfid?09/05 U9280M-H 4. electrical characteristics ? common features U9280M-H operating temperature range: ?40 c to +85 c operating voltage range (v batt ): 2.0v to 6.5v ? low power consumption: ? 600 a at 6.5v in operating mode (with 2 s instruction cycle) ? 200 a at 2.0v in operating mode (with 2 s instruction cycle) ? 1 a at 2.0v in stop mode power supply: contactless (coil 125 khz) and battery supply 5. absolute maximum ratings stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress ra ting only and functional operation of the device at any condition above those indicated in the operati onal section of this specifica tion is not implied. exposure to absolute maximum rating condition for an ex tended period may affect device reliability. all inputs and out puts are protected against high electrosta tic voltages or electric fields. however, precautions to minimize the build-up of electrostati c charges during handling are recommended. reliability of operation is enhan ced if unused inputs are connected to an appropriate logic vo ltage level (e.g., v dd ). voltages are given relative to v ss parameters symbol value unit supply voltage v batt ,v dd 0 to +7 with reverse protection v maximum current out of the v ss pin 15 ma maximum current out of the v batt pin 15 ma input voltage (on any pin) v in v ss ? 0.6 < v in < v dd + 0.6 v input/output clamp current (v ss > v i /v o > v dd )i ik /iok 15 ma minimum esd protection (100 pf through 1.5 k ? )2kv minimum esd protection coil 1 and coil 2 inputs (100 pf through 1.5 k ? ) 1 kv operating temperature range t amb ?40 to +85 c storage temperature range t stg ?40 to +125 c soldering temperature (t 10s) t sd 260 c 6. thermal resistance parameters symbol value unit junction ambient sso20 r thja 140 k/w
16 4591b?rfid?09/05 U9280M-H 7. common dc characteristics v ss = 0v, t amb = ?40c to +85c unless otherwise specified parameters test conditions/pins symbol min. typ. max. unit power supply operating voltage at v batt v batt 2.0 6.5 v operating voltage at v dd v dd v por 6.5 v active current cpu active f syscl = 1 mhz v dd = 2.0v i dd 200 250 a v dd = 3.0v 300 a v dd = 6.5v 600 800 a power down current (cpu sleep, rc oscillator active, 4-mhz quartz oscillator active) f syscl = 1 mhz 1.0 v dd = 2.0v i pd 40 70 a v dd = 3.0v 100 a v dd = 6.5v 250 400 a sleep current (cpu sleep, 32-khz quartz-oscillator inactive 4-mhz quartz-oscillator inactive) v dd = 6.5v i sleep 1.0 2.0 a reset current v dd < v por i reset 150 a 8. dc characteristics ? microcontroller atar092 v ss = 0v, t amb = ?40c to +85c unless otherwise specified parameters test conditions/p ins symbol min. typ. max. unit brown-out protection reset threshold voltage reset threshold voltage bot = 1 v por 155 1.7 1.85 v reset threshold voltage bot = 0 v por 1.85 2.0 2.2 v reset hysteresis v por 50 mv voltage monitor threshold voltage vm high threshold voltage v dd > vm, vms = 1 v mthh 3.0 3.25 v vm high threshold voltage v dd < vm, vms = 0 v mthh 2.8 3.0 v vm middle threshold voltage v dd > vm, vms = 1 v mthm 2.6 2.8 v vm middle threshold voltage v dd < vm, vms = 0 v mthm 2.4 2.6 v vm low threshold voltage v dd > vm, vms = 1 v mthl 2.2 2.4 v vm low threshold voltage v dd < vm, vms = 0 v mthl 2.0 2.2 v external input voltage vmi rising edge threshold vms = 1, v dd = 3v v vmi 1.3 1.4 v vmi falling edge threshold vms = 0, v dd = 3v v vmi 1.2 1.3 v
17 4591b?rfid?09/05 U9280M-H note: the bp20/nte pin has a strong pull-up resistor during the reset-phase of the microcontroller. all bi-directional ports input voltage low v dd = 1.8v to 6.5v v il v ss 0.2 v dd v input voltage high v dd = 1.8v to 6.5v v ih 0.8 v dd v dd v input low current (pull-up) v dd = 2.0v, v dd = 3.0v, v il = v ss v dd = 6.5v i il ?2.0 ?50 ?4.0 ?20 ?100 ?12 ?200 a a a input high current (pull-down) v dd = 2.0v, v dd = 3.0v, v ih = v dd v dd = 6.5v i ih 2.0 50 4.0 20 100 12 200 a a a input low current (strong pull-up) v dd = 2.0v, v il = v ss v dd = 6.5v i il ?20 ?300 ?50 ?600 ?100 ?1200 a a input low current (strong pull-down) v dd = 2.0v, v ih = v dd v dd = 6.5v i ih 20 300 50 600 100 1200 a a input leakage current v il = v ss i il 100 na input leakage current v ih = v dd i ih 100 na output low current v ol = 0.2 v dd v dd = 2.0v v dd = 3.0v, v dd = 6.5v i ol 0.6 8 1.2 5 15 2.5 22 ma ma ma output high current v oh = 0.8 v dd v dd = 2.0v v dd = 3.0v, v dd = 6.5v i oh ?0.6 ?8 ?1.2 ?5 ?16 ?2.5 ?24 ma ma ma 8. dc characteristics ? microc ontroller atar092 (continued) v ss = 0v, t amb = ?40c to +85c unless otherwise specified parameters test conditions/p ins symbol min. typ. max. unit
18 4591b?rfid?09/05 U9280M-H 9. ac characteristics ? operation cycle time supply voltage v dd = 1.8v to 6.5v, v ss = 0v, t amb = ?40c to +85c unless otherwise specified parameters test conditions/pins symbol min. typ. max. unit system clock cycle v dd = 1.8v to 6.5v t amb = ?40c to +85c t syscl 500 2000 ns v dd = 2.4v to 6.5v t amb = ?40c to +85c t syscl 250 2000 ns timer 2 input timing pin t2i timer 2 input clock f t2i 5mhz timer 2 input low time t t2il 100 ns timer 2 input high time t t2ih 100 ns timer 3 input timing pin t3i timer 3 input clock f t3i syscl/2 timer 3 input low time t t3il 2 t syscl ns timer 3 input high time t t3ih 2 t syscl ns interrupt request input timing interrupt request low time t irl 100 ns interrupt request high time t irh 100 ns external system clock exscl at osc1 ecm = en rise/fall time < 10 ns f exscl 0.5 4 mhz exscl at osc1 ecm = di rise/fall time < 10 ns f exscl 0.02 4 mhz input high time rise/fall time < 10 ns t ih 0.1 s reset timing power-on reset time v dd > v por t por 1.5 5 ms rc oscillator 1 frequency f rcout1 3.8 mhz stability v dd = 2.0v to 6.5v ? f/f 50 % temperature coefficient ? f/f/c 0.15 % rc oscillator 2 ? external resistor frequency r ext = 170 k ? r ext = 720 k ? f rcout2 f rcout2 4 1 mhz stability v dd = 2.0v to 6.5v ? f/f 15 % stabilization time t s 10 s 4-mhz crystal oscillator (operating range 2.2v to 6.5v) frequency f x 4mhz start-up time t sq 5ms stability ? f/f ?10 +10 ppm integrated input/out put capacitances (mask programmable) c in /c out programmable in steps of 2 pf c in c out 0 0 20 20 pf pf
19 4591b?rfid?09/05 U9280M-H figure 9-1. crystal and equivalent circuit 32-khz crystal oscillator (ope rating range 2.0v to 6.5v) frequency f x 32.768 khz start-up time t sq 0.5 s stability ? f/f ?10 +10 ppm integrated input/out put capacitances (mask programmable) c in /c out programmable in steps of 2 pf c in c out 0 0 20 20 pf pf external 32-khz crystal parameters crystal frequency f x 32.768 khz serial resistance rs 30 50 k ? static capacitance c0 1.5 pf dynamic capacitance c1 3 ff external 4 mhz crystal parameters crystal frequency f x 4.0 mhz serial resistance rs 40 150 ? static capacitance c0 1.4 3 pf dynamic capacitance c1 3 ff 9. ac characteristics ? operat ion cycle time (continued) supply voltage v dd = 1.8v to 6.5v, v ss = 0v, t amb = ?40c to +85c unless otherwise specified parameters test conditions/pins symbol min. typ. max. unit l c1 rs c0 oscin oscout equivalent circuit sclin sclout l c1 rs c0 oscin oscout equivalent circuit sclin sclout
20 4591b?rfid?09/05 U9280M-H 10. dc characteristics ?trans ponder interface u3280m supply voltage v dd = 1.8v to 6.5v, v ss = 0v, t amb = ?40c to +85c unless otherwise specified parameters test conditions/pins symbol min. typ. max. unit power supply operating voltage at v batt v batt 2.0 6.5 v operating voltage at v dd during battery supply v ddb v batt ? v sd v v dd limiter voltage during coil supply v ddc 2.4 2.9 3.2 v power management field on detection voltage v dd > 1.8v v fdon 2.2 2.5 2.9 v field off detection voltage v dd > 1.8v v fdoff 0.8 v voltage drop at power-supply switch i s = 1 ma, v batt = 2v v sd 300 mv coil input coil 1, coil 2 coil input current i ci 20 ma coil voltage stroke during modulation v cu > 5v v cms 1.8 4.0 v input capacitance c in 30 pf mod pin input low voltage v il v ss 0.2 v dd v input high voltage v ih 0.8 v dd v dd v input leakage current i ileak 10 na ngap/fc pin output low current v dd = 2.0v v ol = 0.2 v dd i ol 0.08 0.2 0.3 ma output high current v dd = 2.0v v oh = 0.8 v dd i oh ?0.06 ?0.15 ?0.25 ma eeprom operating current during erase/write cycle v dd = 2v i wr 450 a
21 4591b?rfid?09/05 U9280M-H 11. ac characteristics ? tran sponder interface u3280m supply voltage v dd = 1.8v to 6.5v, v ss = 0v, t amb = ?40c to +85c unless otherwise specified parameters test conditions symbol min. typ. max. unit serial interface timing (internal) scl clock frequency (intern) f sc 500 khz serial timing (if scl an d sda available extern) scl clock frequency (extern) f scl 0 100 khz clock low time t low 4.7 s clock high time t high 4.0 s sda and scl rise time t r 1000 ns sda and scl fall time t f 300 ns start condition setup time t susta 4.7 s start condition hold time t hdsta 4.0 s data input setup time t sudat 250 ns data input hold time t hddat 0ns stop condition setup time t susto 4.7 s bus free time t buf 4.7 s input filter time t i 100 ns data output hold time t dh 300 1000 ns coil inputs coil frequency f coil 125 khz gap detection delay field off to gap = 0 v coilgap < 0.7 v dc t fgap0 10 50 s delay field on to gap = 1 v coilfield > 3 v dc t fgap1 110s power management battery to field switch delay t bfs 160 650 s field to battery switch delay t fbs 10 60 ms eeprom endurance erase/write- cycles ed 500,000 1,000,000 e/w- cycles data erase/write cycle time for 16 bits access t dew 912ms data erase time t de 2 1/2 t dew ms data retention time t amb = 25c t dr 10 years power-up to read operation t pur 0.2 ms power-up to write operation t puw 0.2 ms
22 4591b?rfid?09/05 U9280M-H file: _____________________ . hex crc: ____________________ . hex aproval date: _________________ signature: _________________________ 12. ordering information please select the option settings from the list below and insert in rom crc. output input output input port 1 port 5 bp10 [x] cmos [x] pull-up bp50 [ ] cmos [ ] pull-up [ ] open drain [n] [ ] pull-down [ ] open drain [n] [ ] pull-down [ ] open drain [p] [ ] pull-up strong [ ] open drain [p] [ ] pull-up strong [ ] pull-down strong [ ] pull-down strong bp13 [x] cmos [x] pull-up bp51 [x] cmos [x] pull-up [ ] open drain [n] [ ] pull-down [ ] open drain [n] [ ] pull-down [ ] open drain [p] [ ] pull-up strong [ ] open drain [p] [ ] pull-up strong [ ] pull-down strong [ ] pull-down strong port 2 bp52 [x] cmos [x] pull-up bp20 [ ] cmos [ ] pull-up [ ] open drain [n] [ ] pull-down [ ] open drain [n] [ ] pull-down [ ] open drain [p] [ ] pull-up strong [ ] open drain [p] [ ] pull- up strong [ ] pull-down strong bp53 [ ] cmos [ ] pull-up bp21 [x] cmos [x] pull-up [ ] open drain [n] [ ] pull-down [ ] open drain [n] [ ] pull-down [ ] open drain [p] [ ] pull-up strong [ ] open drain [p] [ ] pull- up strong [ ] pull-down strong [ ] pull-down strong port 6 bp22 [x] cmos [x] pull-up bp60 [ ] cmos [ ] pull-up [ ] open drain [n] [ ] pull-down [ ] open drain [n] [ ] pull-down [ ] open drain [p] [ ] pull-up strong [ ] open drain [p] [ ] pull-up strong [ ] pull-down strong [ ] pull-down strong bp23 [ ] cmos [ ] pull-up bp63 [ ] cmos [ ] pull-up [ ] open drain [n] [ ] pull-down [ ] open drain [n] [ ] pull-down [ ] open drain [p] [ ] pull-up strong [ ] open drain [p] [ ] pull-up strong [ ] pull-down strong [ ] pull-down strong port 4 bp40 [ ] cmos [ ] pull-up osc1 [ ] open drain [n] [ ] pull-down [ ] no integrated capacitance [ ] open drain [p] [ ] pull-up strong [ ] internal capacitance [ _____pf] [ ] pull-down strong osc2 bp41 [ ] cmos [ ] pull-up [ ] no integrated capacitance [ ] open drain [n] [ ] pull-down [ ] internal capacitance [ _____pf] [ ] open drain [p] [ ] pull-up strong [ ] pull-down strong ecm (external clock monitor) bp42 [ ] cmos [ ] pull-up [ ] enable [ ] open drain [n] [ ] pull-down [ ] disable [ ] open drain [p] [ ] pull-up strong [ ] pull-down strong bp43 [ ] cmos [ ] pull-up [ ] open drain [n] [ ] pull-down [ ] open drain [p] [ ] pull-up strong [ ] pull-down strong
23 4591b?rfid?09/05 U9280M-H 13.1 customer rom mask to be defined by the customer lead time: 18 weeks after rom mask programming and reception of the order 13.2 flash version as flash version of the U9280M-H the marc 4 atar892 is used (available from stock). 14. package information 15. revision history 13. ordering information (continued) extended type number package remarks U9280M-H-xxxz-fsg3y sso20 > 200 kpcs an nually taped and reeled, pb-free technical drawings according to din specifications package sso20 dimensions in mm 6.75 6.50 0.25 0.65 5.85 1.30 0.15 0.05 5.7 5.3 4.5 4.3 6.6 6.3 0.15 20 11 110 please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. revision no. history 4591b-rfid-09/05 ? put datasheet in a new template ? pb-free logo on page 1 added ? ordering information on page 23 changed
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